An FPGA-based digital-to-analog converter engineered from first principles. No off-the-shelf chips. No compromises. No shortcuts.
Concept — Brushed Aluminium
Concept — Obsidian Edition
Concept — Nero Portoro Edition
Enclosure design concepts. Final form factor in development.
The BELLA DAC 1 runs a custom signal processing pipeline entirely inside a Xilinx Artix-7 FPGA. The audio signal passes through a 507,904-tap polyphase FIR reconstruction filter before reaching the PAWS output stage (Parallel Analog Weighted Summation). No delta-sigma modulator chip. No generic DSP. Every multiply, every accumulate, every output pulse is defined in our own RTL.
INPUT PCM / DSD via USB Audio Class 2.0, S/PDIF Up to 24-bit, 16 kHz to 768 kHz FILTER GOAT — Generalized Optimal Aperture Taper Custom polyphase sinc reconstruction FIR 507,904 coefficients, 25×32-bit native multiply Custom coefficient generation (MATLAB) SHAPING 9th+ order sigma-delta noise shaper Custom topology, multi-stage modulation OUTPUT PAWS — Parallel Analog Weighted Summation 2×20 element resistor array Differential, inherently linear Multi-rate: 256×, 128×, 64×, 32×, 16× Analog reconstruction via passive filtering CONNECT XLR balanced output (L/R) RCA unbalanced output (L/R) 6.35mm headphone output PLATFORM Xilinx Artix-7 XC7A200T FPGA Custom multi-layer PCB OLED display, rotary encoder, IR remote
Commercial DAC chips (ESS, AKM, Burr-Brown) impose fixed architectures and known limitations. The BELLA DAC 1 implements the entire digital-to-analog conversion in programmable logic. Every parameter is tunable. Every trade-off is ours to make.
The custom sinc reconstruction FIR filter runs 507,904 taps across 256 polyphase stages. This is not a marketing number. It is the actual number of multiply-accumulate operations performed on every sample. The result: near-perfect impulse response with no pre-ringing artifacts.
20 identical elements per channel, running simultaneously. Each element's PWM duty cycle determines its contribution. Summed into a single analog output. Signal-independent switching activity. Inherently linear. The cat has paws.
The FPGA bitstream is field-updatable. Filter profiles, noise shaper topology, output stage configuration, and oversampling rates can be modified after purchase. The hardware grows with the firmware.
“If it doesn’t exist, build it yourself.”— Pretty Good DACs founding principle
We are currently finalizing the hardware design and preparing for initial production. Join the waitlist to be notified when the BELLA DAC 1 is available.
For partnerships or distribution: dan@prettygooddacs.com